Freescale Semiconductor /MKL28T7_CORE1 /SIM /PCSR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as PCSR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)CS1 0 (0)CS2 0 (0)CS3 0 (0)CS4 0 (0)CS5 0 (0)CS6 0 (0)CS7

CS1=0, CS3=0, CS7=0, CS5=0, CS2=0, CS6=0, CS4=0

Description

Peripheral Clock Status Register

Fields

CS1

Clock Source 1

0 (0): Clock not ready.

1 (1): Clock ready.

CS2

Clock Source 2

0 (0): Clock not ready.

1 (1): Clock ready.

CS3

Clock Source 3

0 (0): Clock not ready.

1 (1): Clock ready.

CS4

Clock Source 4

0 (0): Clock not ready.

1 (1): Clock ready.

CS5

Clock Source 5

0 (0): Clock not ready.

1 (1): Clock ready.

CS6

Clock Source 6

0 (0): Clock not ready.

1 (1): Clock ready.

CS7

Clock Source 7

0 (0): Clock not ready.

1 (1): Clock ready.

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